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跪求大虾转换下VHDL→verilog,QuartusII里生成不了VHDL文件

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故无法用XHDL转换了……
--扫描信号发生器
COUNTER : BLOCK IS
SIGNAL Q: STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL SEL: STD_LOGIC_VECTOR (3 DOWNTO 0);
--1110-1101-1011-0111
BEGIN
PROCESS (CLK_1K) IS
BEGIN
IF CLK_1K'EVENT AND CLK_1K ='1' THEN
Q <= Q+1;
END IF;
C_DEBOUNCE <= Q(2) ; --去抖时钟信号, 大约125 Hz
C_KEYBOARD <= Q(2 DOWNTO 1) ;
-- 产生键扫信号***“00-01-10-11”, 大约16 Hz
--C_DEBOUNCE <= Q(1) ; --仿真时用
--C_KEYBOARD <= Q(5 DOWNTO 4) ; --仿真时用
CLK <= Q(0) ;
END PROCESS;
CLK_DEBOUNCE<=C_DEBOUNCE;
SEL <= "1110" WHEN C_KEYBOARD=0 ELSE
"1101" WHEN C_KEYBOARD=1 ELSE
"1011" WHEN C_KEYBOARD=2 ELSE
"0111" WHEN C_KEYBOARD=3 ELSE
"1111";
CLK_SCAN <= SEL ;
END BLOCK COUNTER ;
还有一段:
--键盘译码
KEY_DECODER : BLOCK
SIGNAL Z : STD_LOGIC_VECTOR(4 DOWNTO 0) ; --按键位置
BEGIN
PROCESS(CLK)
BEGIN
Z <= C_KEYBOARD & C ;
IF CLK'EVENT AND CLK = '1' THEN
CASE Z IS
WHEN "11101" => N <= "0000" ; --0
WHEN "00011" => N <= "0001" ; --1
WHEN "00101" => N <= "0010" ; --2
WHEN "00110" => N <= "0011" ; --3
WHEN "01011" => N <= "0100" ; --4
WHEN "01101" => N <= "0101" ; --5
WHEN "01110" => N <= "0110" ; --6
WHEN "10011" => N <= "0111" ; --7
WHEN "10101" => N <= "1000" ; --8
WHEN "10110" => N <= "1001" ; --9
WHEN OTHERS => N <= "1111" ;
END CASE ;
END IF ;


IP属地:四川1楼2012-05-25 13:44回复
    哈哈、;2356650356:QQ


    43楼2012-08-23 21:35
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